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rev.01 1/33 64mb sdram ordering information em 48 2m 32 4 4 v t a ? 5 l eorex logo edo/fpm : 40 d-rambus : 41 ddrsdram : 42 ddrsgram : 43 sgram : 46 sdram : 48 f : pb free package power blank : standard l : low power i : indus trial density 16m : 16 mega bits 8m : 8 mega bits 4m : 4 mega bits 2m : 2 mega bits 1m : 1 mega bit refresh 1 : 1k, 8 : 8k 2 : 2k, 6 :16k 4 : 4k bank 2 : 2bank 6 : 16bank 4 : 4bank 3 : 32bank 8 : 8bank revision a : 1s t b : 2nd c : 3rd d : 4 th g: fo r vga ve rs i o n o n l y interface v : 3.3v r : 2.5v package min cycle time ( max freq.) -5 : 5ns ( 200mhz ) -6 : 5ns ( 167mhz ) -7 : 7ns ( 143mhz ) -75 : 7.5ns ( 133mhz ) -8 : 8ns ( 125mhz ) -10 : 10ns ( 100mhz ) c: csp b: ubga t: tsop q: tqfp p: pqfp ( qfp ) l: lqfp organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 url: http://www.eorex.com email: sales@eorex.com
rev.01 2/33 64mb sdram features ? fully synchronous to positive clock edge ? single 3.3v +/- 0.3v power supply ? lvttl compatible with multiplexed address ? programmable burst length ( b/ l ) - 1,2,4,8 or full page ? programmable cas latency ( c/ l ) - 2 or 3 ? data mask ( dqm ) for read/write masking ? programmable wrap sequential - sequential ( b/ l = 1/2/4/8/full page ) - interleave ( b/ l = 1/2/4/8 ) ? burst read with single-bit write operation ? all inputs are sampled at the positive rising edge of the system clock. ? auto refresh and self refresh ? 4,096 refresh cycles / 64ms description the em482m3244vta is synchronous dynamic random access memory ( sdram ) organized as 524,288 words x 4 banks x 32 bits. all inputs and outputs are synchronized with the positive edge of the clock . the 64mb sdram uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3v low power memory system. it also provides auto refresh with power saving / down mode. all inputs and outputs voltage levels are compatible with lvttl . * eorex reserves the right to change products or specification without notice. 64mb( 4banks ) synchronous dram em482m3244vta (2mx32)
rev.01 3/33 64mb sdram 86pin tsop-ii (400mil x 875 mil) (0.5mm pin pitch) pin assignment ( top view ) v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v dd dqm0 /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 dqm2 v dd nc dq16 v ssq dq17 dq18 v ddq dq19 dq20 v ssq dq21 dq22 v ddq dq23 v dd v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc vss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v ddq dq30 dq29 v ssq dq28 dq27 v ddq dq26 dq25 v ssq dq24 v ss 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
rev.01 4/33 64mb sdram pin na me pin function clk system clock master clock input(active on the positive rising edge) /cs chip select selects chip when active cke clock enable activates the clk when ?h? and deactivates when ?l?. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a0 ~ a10 ad d re s s row address (a0 to a10) is determined by a0 to a10 level at the bank active command cycle clk rising edge. ca(ca0 to ca7) is determ ined by a0 to a7 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the pre-charge mode. when a10 = high at the pre-charge command cycle, all banks are pre-charged. but when a10 = low at the pre-charge command cycle, only the bank that is selected by ba is pre-charged. /ras row address strobe latches row addresses on the positive rising edge of the clk with /ras ?l?. enables row access & pre-charge. /cas column address strobe latches column addresses on the positive rising edge of the clk with /cas low. enables column access. /we write enable latches column addresses on the positive rising edge of the clk with /cas low. enables column access. dqm0 ~ dqm3 data input/output mas k dqm controls i/o buffers. dq0 ~ 31 data input/output dq pins have the same function as i/o pins on a conventional dram. v dd /v ss power supply/ground v dd and v ss are power supply pins for internal circuits. pin descriptions ( simplified ) ba0~ba1 bank address selects which bank is to be active. nc no connection this pin is recommended to be left no connection on the device. v ddq /v ssq power supply/ground v ddq and v ssq are power supply pins for the output buffers.
rev.01 5/33 64mb sdram burst counter row add. buffer col. add. buffer col. decoder s/a & i/o gating block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ba0 ba1 timing register cke /cs /ras /cas /we dqm row decoder memory array address register mode register set auto/self refresh counter col. add. counter write dqm control data in data out read dqm control dqi dqm dqm clk /clk
rev.01 6/33 64mb sdram commands the em482m3244vta have a mode register that defines how the device operates. in this command, a0 through ba are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when all banks are in idle state. the eo482m3244vta, cannot accept any other commands,only during 2clk can following this command. ( figure. 1 mode register set command ) mode register set command ( /cs, /ras, / cas, /we = low ) the em482m3244vta have 4 banks, each with 2,048 rows. this command activates the bank selected by ba and a row address selected by a0 through a10.this command corresponds to a conventional dram?s /ras falling. ( figure. 2 row address strobe and bank activate command ) active command ( /cs, /ras = low , /cas, /we = high ) ad d /cs clk /ras /cas /we ba a1 0 cke ? h ? ad d /cs clk /ras /cas /we ba a1 0 cke ? h ? row row
rev.01 7/33 64mb sdram this command begins precharge operation of the ban k selected by. when a10 is high,all banks are precharged, regardless of. when ba is low,only the bank selected by ba is precharged. ( figure. 3 precharged command ) precharge command ( /cs, /ras, /we = low , / cas = high ) ad d /cs clk /ras /cas /we ba a1 0 cke ? h ? if the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. the first write data in burst mode can input with this command with subsequent data on following clicks. ( figure. 4 column address and write command ) write command ( /cs, /cas, /we = low, /ras = high ) ad d /cs clk /ras /cas /we ba a1 0 cke ? h ? column
rev.01 8/33 64mb sdram raed data is available after /cas latency requirements have been met. this command sets the burst start address given by the column. ( figure. 5 column address and read command ) read command ( /cs, /cas = low , / ras, /we = high ) ad d /cs clk /ras /cas /we ba a1 0 cke ? h ? this command is a request to begin the cbr refresh operation. the refresh address is generated internally. before executing cbr refresh, all banks must be precharged. after this cycle, all banks will be in the idle (precharged ) state and ready for a row activate command. during t r c period ( from refresh command to refresh or activate command ), the em482m3244vta cannot accept an y other command. ( figure. 6 auto refresh command ) auto refresh command ( /cs, /ras, /cas = low, /we, cke = high ) ad d /cs clk /ras /cas /we ba a1 0 cke ? h ? column
rev.01 9/33 64mb sdram after the command execution, self refresh operation continues while cke remains low. when cke goes high, the memory exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there before is no need for external control. before executing self refresh, both banks must be precharged. ( figure. 7 self refresh entry command ) self refresh entry command ( /cs, / ras , /cas, cke = low , /we = high ) ad d /cs clk /ras /cas /we ba a1 0 cke this command can stop the current burst operation. ( figure. 8 burst stop command in full page mode ) burst stop command ( /cs, /we = low, /ras, /cas = high ) ad d /cs clk /ras /cas /we ba a1 0 cke ? h ?
rev.01 10/33 64mb sdram this command is not execution command so there is no operations begin or terminate by this command. ( figure. 9 no operation ) no operation ( /cs = low, / ras , /cas, /we = high ) ad d /cs clk /ras /cas /we ba a1 0 cke initialization ? h ? the synchronous dram is initialized in the power-on sequence according to the following: 1. to stabilize internal circuits, when power is applied, a 100us or longer pause must precede any signal toggling. 2. after the pause, both banks must be precharged using the precharged command ( the precharge all banks command is convenient ). 3. once the precharge is completed and the minimum t rp is satisfied, the mode register can be programmed. 4. two or more arto refresh must be performed. remanks: 1. the sequence of mode register programming and refresh above may be transposed. 2. cke and dqm must be held high until the precharge command is issued to ensure data-bus hi-z.
rev.01 11/33 64mb sdram programming the mode register the mode register is programmed by the mode register set command using address bits ba through a0 as data inputs. the register retains data until it is reprogrammed or the device loses power. ba through a7 options /cas latency a6 through a4 wrap type a3 burst length a2 through a0 following mode register programming, no command can be issued before at least 2 clk elapsed. /cas latency /cas latency is the most critical of the parameters begin set. it tells the device how many clocks must elapse before the data will be available. burst length burst length is the number of the words that will be output or input in a write cycle. after a read burst is completed, the output bus will become hi-z. the burst length is programmable as 1,2,4,8 or full page. wrap type ( burst sequence ) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either sequence or interleave. the method chosen will depend on the type of cpu in the system. some microprocessor cache systems are optimized for sequential addressing and others for interleaved.
rev.01 12/33 64mb sdram idle row acti ve acti ve power down power down cbr refresh self refresh mo d e register set write writea read reada read suspend reada suspend write suspend writea suspend precharge power on simplified state diagram s e l f s e l f e x i t r e f m r s c k e c k e a c t c k e c k e b s t r e a d r e a d c k e c k e c k e c k e w r i t e r e a d w r i t e w i th r e a d w i t h c k e c k e c k e c k e p r e c h a r g e p r e p r e w r i t e m a n u a l i n p u t a u t o m a t i c s e q u e n c e
rev.01 13/33 64mb sdram ba0/1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length a2 a1 a0 sequential burst length interleave 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved a3 0 burst type interleave 1 sequential a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ba0/1 a10 a9 a8 a7 0 0 0 0 0 0 0 1 0 0 operation mode normal burst read with single-bit write address input for mode register set
rev.01 14/33 64mb sdram a2 a1 a0 interleave addressing burst length x x 0 0 1 2 x x 1 1 0 x 0 0 0 1 2 3 4 x 0 1 1 0 3 2 x 1 0 2 3 0 1 x 1 1 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 8 0 0 1 1 0 3 2 5 4 7 6 burst type ( a3 ) sequential addressing 0 1 1 0 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 0 1 0 2 3 0 1 6 7 4 5 0 1 1 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 1 0 1 5 4 7 6 1 0 3 2 1 1 0 6 7 4 5 2 3 0 1 1 1 1 7 6 5 4 3 2 1 0 n n n - 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 cn cn+ 1 cn+ 2 ?... full page * * page length is a function of i/o organization and column addressing x32 (ca0 ~ ca7) : full page = 256 bits
rev.01 15/33 64mb sdram precharge the precharge command can be issued anytime after t ras ( min.) is satisfied. soon after the precharge command is issued, precharge operation performed and the synchronous dram enters the idle state after t rp is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharege command can be issued without losing any data in the burst is as follows. it is depends on the /cas latency and clock cycle time. in order to write all data to the memory cell correctly, the asynchronous parameter t dpl must be satisfied. the t dpl (min.) specification defines the eariliest time that a precharge command can be issued. minimum number of clocks is calculated by dividing t dpl (min.) with clock cycle time. in a word, the precharge command can be issued relative to reference clock that indicates the last data word is valid. the minus in the following table means clocks before the reference and the plus means time after the reference. 2 /cas latency 3 -1 read -2 + t dpl ( min.) write + t dpl ( min.) clk 012345678 command ( cl= 2 ) dq ( cl= 2 ) command ( cl= 3 ) dq ( cl= 3 ) read pre q3 q4 hi-z q1 q2 read pre hi-z q3 q4 q1 q2 b l = 4
rev.01 16/33 64mb sdram auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. a10 high in the read or write command ( read with auto precharge command or write with auto precharge command ), auto precharge is selected and begins automatically. the t ras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started , an activate command to the bank can be issued after t rp has been satisfied re ma nks: read ap means read with auto precharge read with auto precharge during a read cycle, the auto precharge begins same as ( /cas latency of 2 ) or one clock earlier ( /cas latency of 3 ) the last data word output. clk 012345678 command ( cl= 2 ) dq ( cl= 2 ) command ( cl= 3 ) dq ( cl= 3 ) read ap q3 q4 hi-z q1 q2 read ap hi-z q3 q4 q1 q2 b l = 4 ( tras must be satisfied ) auto precharge starts auto precharge starts
rev.01 17/33 64mb sdram remanks: write ap means write with auto precharge write with auto precharge during write cycle, the auto precharge starts at the timing that is equal to the value o f the t dpl ( min.) after the last dataword input to the device. clk 012345678 command ( cl= 2 ) dq ( cl= 2 ) command ( cl= 3 ) dq ( cl= 3 ) wr ite ap hi-z wr ite ap hi-z b l = 4 ( tras must be satisfied ) d3 d4 d1 d2 d3 d4 d1 d2 auto precharge starts auto precharge starts tdpl( min. ) tdpl( min. ) in summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. in the following table minus means clocks before the reference ,plus means after the reference. 2 /cas latency 3 -1 read -2 + t dpl ( min.) write + t dpl ( min.)
rev.01 18/33 64mb sdram read to read command interval b l = 4, c l = 2 read / write command interval during a read cycle, when new read command is issued,it will be effective after / cas latency, even if the previous read operation does not completed. read will be interrupted by another read. the interval between the commands is 1 cycle minimum. each read command can be issued in every clock without any restriction. clk 012345678 command dq r ead a hi-z qb2 qb3 qa1 qb1 1 cycle read b qb4 during a write cycle, when new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. write will be interrupted by another write. the interval between the commands is minimum 1 cycle. each write command can be issued in every clock without any restriction. clk 012345678 command dq write a hi-z 1 cycle wr i te b db2 db3 da1 db1 db4 write to write command interval b l = 4, c l = 2
rev.01 19/33 64mb sdram write to read command interval b l = 4 write and read command interval is also 1 cycle. only the write data before read command will be written. the data bus must be hi-z at least one cycle prior to the first d out . clk 012345678 command ( cl = 2 ) dq ( cl = 2 ) command ( cl = 3 ) dq ( cl = 3 ) wr ite a hi-z qb2 qb3 da1 qb1 read b qb4 wr ite a hi-z da1 read b qb2 qb3 qb1 qb4
rev.01 20/33 64mb sdram read to write command interval during a read cycle, read can be interrupt by write. the read and write command interval is 1 cycle minimum. there?s a restriction to avoid data conflict. the data bus must be hi-z using dqm before write. b l = 8 command ( cl = 3 ) dq ( cl = 3 ) dqm hi-z is necessar y d2 d3 d1 q1 q2 read wr i te clk 012345678 command ( cl = 2 ) read wr i te dq ( cl = 2 ) dqm 9 hi-z is necessar y d2 d3 d1 q2 q3 q1 clk 012345678 command read wr ite dq dqm 9 hi-z d3 d3 d2 d1 read can be interrupted by write. dqm must be high at least 3 clicks prior to the write command. b l = 4
rev.01 21/33 64mb sdram burst stop command there are two ways to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. burst terminate during a read cycle,when the burst stop command is issued, the burst read are terminated and the data bus goes to hi-z after the /cas latency from the burst stop command. during a write cycle,when the burst stop command is issued, the burst write data are terminated and the data bus goes to hi-z at the same clock with the burst stop command. clk 012345678 command read burst stop dq ( cl = 3 ) dq ( cl = 2 ) 9 hi-z q3 q2 q1 b l = don?t care q3 q2 q1 hi-z clk 012345678 command wr ite burst stop dq ( cl = 2 /3 ) 9 hi-z b l = don?t care d4 d3 d2 d1
rev.01 22/33 64mb sdram precharge termination during a read cycle, the burst read operation is terminated by a precharge command. when the precharge command is issued, the burst read operation is terminated and precharge starts. the same banks can be activated again after t rp from the precharge command. to issue a precharge command , t ra s must be satisfied. when /cas latency is 3, the read data will remain valid until two clocks after the precharge command. command dq hi-z precharge termination in read cycle when /cas latency is 2, the read data will remain valid until two clocks after the precharge command. b l = don?t care , cl= 3 clk 012345678 read pre- char g e 9 activ e q3 q2 q1 q4 b l = don?t care , cl= 2 clk 012345678 read pre- char g e 9 q3 q2 q1 active q4 t rp t rp command dq hi-z
rev.01 23/33 64mb sdram during a write cycle, the burst write operation is terminated by a precharge command. when the precharge command is issued, the burst write operation is terminated and precharge starts. the same banks can be activated again after t rp from the precharge command. to issue a precharge command , t ra s must be satisfied. precharge termination in write cycle when /cas latency is 2, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. in order to avoid this situation, dqm must be high at the same clock as the precharge command. this will mask the invalid data. when /cas latency is 3, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. in order to avoid this situation, dqm must be high at the same clock as the precharge command. this will mask the invalid data. command hi-z clk 012345678 write pre- char g e 9 active dq b l = don?t care, cl= 2 ( tras must be satisfied ) d1 t rp dqm d3 d2 d4 d5 command hi-z clk 012345678 write pre- charge 9 activ e dq d1 t rp dqm d3 d2 d4 d5 b l =don?t care , cl= 3 ( tras must be satisfied )
rev.01 24/33 64mb sdram command symbol cke ignore command desl no operation nop truth table 1. command truth table ( em482m3244vta ) h h x n-1 n /cs h l x /ras x h /cas x h /we x h burst stop bsth read rea d h h x l l x h h h l l h read with auto pre-charge rea da write writ h h x l l x h h l l h l write with auto pre-charge writa bank activate act h h x l l x l l h h h h pre-charge select bank pre h l x l h l pre-charge all banks pa l l mode register set mrs h h x l l x l l h l l l a10 x x x l h l h v l h l a9~a0 x x x v v v v v x x v no t e : h = high level, l = low level, x = high or low level (don't care), v = valid data input command symbol cke data w rite / output enable enb data mask / output disable ma sk 2. dqm truth table h h x n-1 n /cs h l x upper byte w rite enable / output enable bsth read rea d h h x l l x read w ith auto pre-charge rea da write writ h h x l l x write w ith auto pre-charge writa bank activate act h h x l l x pre-charge select bank pre h l x pre-charge all banks pa l l mode register set mrs h h x l l x no t e : h = high level, l = low level, x = high or low level (don't care), v = valid data input command symbol cke acti va ti n g an y 3. cke truth table h l l n-1 n /cs x x l /ras x x /cas x x /we x x addr. x x clock suspend idle ref l h h x l h x l x l x h x x idle self self refres h h l l l l h l h l h h h x x idle power down h l l x x h x x x x x x x x re m ar k h = high level, l = low level, x = high or low level (don't care) command clock suspend mode entry clock suspend mode clock suspend mode exit cbr refresh command self refresh entry self refresh exit pow er dow n entry pow er dow n exit l h h x x x x ba x x x v v v v v v x l
rev.01 25/33 64mb sdram current state addr. idle x x 4. operative command table action nop or pow er dow n nop or pow er dow n notes 2 2 ba/ca/a10 ba/ca/a10 illegal illegal 3 3 ba/ra row activating ba, a10 x nop refresh or self refresh 4 re m ar k h = high level, l = low level, x = high or low level (don't care) /cs h l /r x h /c x h /w x x l l h h l l h l l l h h l l l l h l l h command desl nop or bst rea d/rea da writ/writa act pre/ pa l l ref/self op-code mode register accessing l l l l mrs row active x x nop nop ba/ca/a10 ba/ca/a10 begin read : determine ap begin w rite : determine ap 5 5 ba/ra illegal 3 ba, a10 x precharge illegal 6 4 h l x h x h x x l l h h l l h l l l h h l l l l h l l h desl nop or bst rea d/rea da writ/writa act pre/ pa l l ref/self op-code illegal l l l l mrs re ad x x continue burst to end row ac tiv e continue burst to end row ac tiv e x ba/ca/a10 burst stop row ac tiv e terminate burst, new read : determine ap 7 ba/ca/a10 terminate burst, start w rite : determine ap 7, 8 ba/ra ba/a 10 illegal terminate burst, pre-charging 3 4 h l x h x h x h l l h h h l l h l l l l l l l l h h h l desl nop bst rea d/rea da writ/writa act pre/ pa l l x illegal l l l h ref/self write x x continue burst to end write recovering continue burst to end write recovering x ba/ca/a10 burst stop row ac tiv e terminate burst, start read : determine ap 7, 8 7,8 ba/ca/a10 terminate burst, new w rite : determine ap 7 7 ba/ra ba/a 10 illegal terminate burst, pre-charging 3 9 h l x h x h x h l l h h h l l h l l l l l l l l h h h l desl nop bst rea d/rea da writ/writa act pre/ pa l l x illegal l l l h ref/self op-code illegal l l l l mrs op-code illegal l l l l mrs
rev.01 26/33 64mb sdram current state addr. re ad w it h ap x x action continue burst to end precharging continue burst to end precharging notes x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x illegal illegal 3 re m ar k h = high level, l = low level, x = high or low level (don't care), ap = auto precharge /cs h l /r x h /c x h /w x h l l h h h l l h l l h h l l l l h l l h command desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa write w ith ap x x burst to end write recovering w ith auto precharge continue burst to end write recovering w ith auto precharge x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x illegal illegal 3 h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa pre charging x x nop enter idle af ter t rp nop enter idle af ter t rp x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x nop enter idle af ter t rp illegal h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa row activating x x nop enter idle af ter t rcd nop enter idle af ter t rcd x ba/ca/a10 illegal illegal 3 ba/ra illegal 3,10 ba, a10 x illegal illegal 3 h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa
rev.01 27/33 64mb sdram current state addr. write recovering x x action nop enter row active af ter t dpl nop enter row active af ter t dpl notes x ba/ca/a10 nop enter row active af ter t dpl start read, determine ap ba/ra illegal 3 ba, a10 x illegal illegal 3 re m ar k h = high level, l = low level, x = high or low level (don't care), ap = auto precharge /cs h l /r x h /c x h /w x h l l h h h l l h l l h h l l l l h l l h command desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 new write, determine ap 8 l h l l writ/writa write recovering with ap x x nop enter precharge after t dpl nop enter precharge after t dpl x ba/ca/a10 nop enter precharge after t dpl illegal 3,8 ba/ra illegal 3 ba, a10 x illegal illegal h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa refreshing x x nop enter idle after t rc nop enter idle after t rc x x illegal illegal h l x h x h x x l l h l l h x x desl nop/ bst rea d/writ a ct/ pre/ pa l l x illegal l l l x ref/self/mrs mode register accessing x x nop nop x x illegal illegal h l x h x h x h l l h h h l l x desl nop bst rea d/writ x illegal l l x x a ct/ pre/ pa l l / ref/self/mrs no t e s 1. all entries assume that cke w as active (high level) during the preceding clock cycle. 2. if all banks are idle, and cke is inactive (low level), sdram w ill enter pow er dow n mode. all input buffers except cke w ill be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba0/1), depending on the state of that bank. 4. if all banks are idle, and cke is inactive (low level), sdram w ill enter self refresh mode. all input buffers except cke w ill be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. must mask preceding data w hich don't satisfy t dpl . 10. illegal if t rrd is not satisfied.
rev.01 28/33 64mb sdram current state addr. se lf re fre s h x x 5. command truth table for cke action invalid, clk (n ? 1) w ould exit self refresh self refresh recovery notes x x self refresh recovery illegal x illegal x maintain self ref resh re m ar k : h = high level, l = low level, x = high or low level (don't care) /cs x h /r x x /c x x /w x x l l h h h l x x l l x x x x x x se lf re fre s h recovery x x idle after t rc idle after t rc x x illegal illegal x illegal x x illegal illegal h l x h x h x x l l h l l x x x h x x x l l h h h l x x x illegal l l x x bo t h b an k s idle refer to operations in operative command table refer to operations in operative command table refer to operations in operative command table x ref r es h op-code refer to operations in operative command table refer to operations in operative command table h l x h x x x x l l h x l l l h l h l x l x l x refer to operations in operative command table l h x x refer to operations in operative command table l l h x n-1 h l l l l l h h h h h h h h h h h h h h h h n x h h h h l h h h h l l l l h h h h h l l l cke pow er dow n x x invalid, clk(n-1) w ould exit pow er dow n exit pow er dow n idle x maintain pow er dow n mode x x x x x x x x x x x x h l l x h l x self ref resh 1 l l l h op-code refer t o operations in operative command table l l l l x pow er dow n 1 x x x x h h l l l x ro w act ive x refer to operations in operative command table x x x x h x x pow er dow n 1 x x x x l x any state other than lis ted above x refer to operations in operative command table begin clock suspend next cycle 2 x exit clock suspend next cycle x maintain clock suspend x x x x x x x x x x x x x x x x h h l l h l h l no t e s 1. self refresh can be entered only from the both banks idle state. pow er dow n can be entered only from both banks idle or row active state. 2. must be legal command as defined in operative command table.
rev.01 29/33 64mb sdram absolute maximum ratings symbol item rating units v in , v out input, output voltage -0.3 ~ 4.6 v v dd , v ddq power supply voltage -0.3 ~ 4.6 v t op operating temperature 0 ~ 70 c t stg storage temperature -55 ~ 150 c p d power dissipation 1 w i os short circuit current 50 ma recommended dc operation condi tions ( ta = 0 ~ 70c) symbol parameter min. units v dd power supply voltage 3.0 v v ddq power supply voltage (for i/o buffer) 3.0 v v ih input logic high voltage 2.0 v v il input logic low voltage -0.3 v no t e : caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating c onditions f or extended periods may af f ect device reliability. typical 3.3 3.3 max. 3.6 3.6 v dd +0.3 0.8 no t e : 1. all voltage referred to v ss . 2. v ih (max) = 5.6v for pulse w idth 3ns 3. v il (min) = -2.0v for pulse w idth 3ns capacitance ( vcc =3.3v, f = 1mhz, ta = 25c ) symbol parameter min. units c clk clock capacitance 2.5 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqm0 ~ 3 2.5 pf max. 4.0 4.5 c o input/output capacitance 4.0 pf 6.5
rev.01 30/33 64mb sdram recommended dc operating conditions ( vdd = 3.3v +/- 0.3 v, ta = 0 ~ 70 c, ta = -40 to 85c for -6i ) no t e : 1. icc1 depends on output loading and cycle rates. specified values are obtained w ith the output open. input signals are changed only one time during tck(min) 2. icc4 depends on output loading and cycle rates. specified values are obtained w ith the output open. input signals are changed only one time during tck(min) 3. input signals are changed only one time during tck(min) 4. standard pow er version. 5. low pow er version. precharge standby current in power down mode precharge standby current in non-power down mode active standby current in non-power down mode operating current (burst mode) refresh current self refresh current active standby current in power down mode cke v il (min), t ck = 15ns, /cs v ih (min) input signals are changed one time during 30ns cke v il (min), t ck = input signals are stable i cc3n i cc3ns cke v il (max.), t ck = operating current parameter test condition burst length = 1, t rc t rc (min), iol = 0 ma, one bank active cke v il (max.), t ck = 15 ns symbol i cc1 i cc2p i cc2ps cke v il (min.), t ck = 15 ns, /cs v ih (min.)input signals are changed one time during 30ns cke v il (min.), t ck = input signals are stable i cc2n i cc2ns t ccd = 2clks , i ol = 0 ma t rc t rc (min.) cke 0.2v i cc4 i cc5 i cc6 cke v il (max), t ck = 15ns cke v il (max), t ck = i cc3p i cc3ps 1 60 30 1 35 10 5 1 0.4 ma ma ma ma units ma notes 1 ma ma ma ma ma 2 3 4 ma ma 5 cl=3 cl=2 1 125 120 190 160 - - -5 -6/6i -7 max -7l 110 110 140 140 - - cl=3 cl=2 - 100 - 90 - 80 - 120
rev.01 31/33 64mb sdram ac operating test conditions ( vdd = 3.3v +/- 0.3 v, ta = 0 ~ 70c ) output reference level 1.4v / 1.4v output load see diagram as below input signal level 2.4v / 0.4v transition time of input signals 2ns input reference level 1.4v z = 50 ? 50pf 50 ? v tt = 1.4v output parameter test condition symbol max. unit min. input leakage current 0 v i v ddq , v ddq =v dd all other pins not under test=0 v i il +0.5 ua -0.5 output leakage current 0 v o v ddq , dout is disabled i ol +0.5 ua -0.5 high level output voltage io = -4m a v oh v 2.4 low level output voltage io = +4m a v ol v 0.4 recommended dc operating conditions ( continued )
rev.01 32/33 64mb sdram operating ac characteristics ( vdd = 3.3v +/- 0.3 v, ta = 0 ~ 70c, ta = -40 to 85c for -6i ) note : 1. all voltages referenced to vs s . 2. t hz defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 3. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows : the number of clock cycles = specified value of timing/clock period (count fractions as a whole number) symbol t ck t ac t ch t cl t oh t hz t lz t is t ih t rc t ras t rp t rcd parameter clock cycle time acces s tim e from clk data-out hold tim e data-out high impedance time clk high level width clk low level width input setup time input hold tim e active to active command period active to precharge command period precharge to active command period ac tive to r ead /wr ite d e l a y ti m e cl = 3 cl = 2 cl = 2 cl = 3 cl = 2 cl = 3 cl = 2 data-out low impedance time cl = 3 cl = 3 units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -6/6i min. max. 7.5 1000 1000 5.5 5.5 6 2 2 2 6 0 1.5 60 42 18 18 100k 1 -5 min. max. 7 1000 1000 5.5 5 4.5 2 2 1.5 5 0 1.5 54 40 18 18 100k 1 -7 min. max. 8 1000 1000 5.5 6 7 2 2 2 7 0 2 65 45 18 18 100k 1 -7l min. 2 7 2 2 2 0 2 65 45 18 18 max. 1000 7 7 5.5 100k 1 notes 2 3 3 3 3 t rrd active(one) to active(another) command ns 12 10 14 16 3 t ccd t dpl t bdl t roh t ref read/write com m and to read/write command data-in to precharge command data-out to high impedance from precharge command data-in to burst stop command refres h tim e(4,096 cycle) cl = 3 cl = 2 1 2 1 3 64 2 clk clk clk clk clk ms 10 1 2 1 3 64 2 1 2 1 3 64 2 1 2 1 3 64 2
rev.01 33/33 64mb sdram * eorex reserves the right to change products or specification without notice. package dimension 11.76 + /- 0.20 0.463 + /- 0.008 ma x 0.10 0.004 0.05 0.002 min 0.21 +/- 0.05 0.008 + /- 0.002 1.00 +/- 0.10 0.039 +/- 0.004 1.20 0.047 ma x 0.61 0.024 0.20 +0.07 / -0.03 0.008 + 0.003 / -0.001 0.50 0.020 22.62 0.891 ma x 22.22 +/- 0.10 0.875 +/- 0.004 0 ? 8 ? 0.25 0.010 ty p 10.16 0.400 0.50 0.020 0.45 ? 0.75 0.018 ? 0.030 0.125 +0.075 / - 0.035 0.005 + 0.003 / -0.001 pin1

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